Integrated rf limiter

ABSTRACT

A limiter circuit is integrated into an RF power amplifier. The limiter circuit automatically starts adding attenuation at the input of the RF power amplifier after a predetermined input power level threshold is exceeded, thereby extending the safe input drive level to protect the amplifier. In a preferred embodiment of the invention, the limiter circuit is implemented using a pseudomorphic high electron mobility transistor (PHEMT) device or a metal semiconductor field effect transistor (MESFET) device. Diode connected transistors or Schottky diodes may also be used in the limiter circuit.

CROSS REFERENCE TO RELATED APPLICATION

This application claims benefit of provisional application Ser. No. 62/087,154, filed Dec. 3, 2014, which application is incorporated by reference herein in its entirety.

BACKGROUND

Radio frequency (RF) power amplifiers are sometimes subjected to input RF overdrive conditions, typically during a calibration procedure for cell phone applications. This overdrive condition can be destructive depending on other factors such as supply voltage and output load voltage standing wave ratio (VSWR).

SUMMARY

A limiter circuit is integrated into an RF power amplifier. The limiter circuit automatically starts adding attenuation at the input of the RF power amplifier after a predetermined input power level threshold is exceeded, thereby extending the safe input drive level to protect the amplifier. In a preferred embodiment of the invention, the limiter circuit is implemented using a pseudomorphic high electron mobility transistor (PHEMT) device or a metal semiconductor field effect transistor (MESFET) device. Diode connected transistors or Schottky diodes may also be used in the limiter circuit.

BRIEF DESCRIPTION OF DRAWING

These and other objects, features and advantages of the invention will be more readily apparent from the following detailed description in which:

FIG. 1 is a block diagram of a first illustrative embodiment of the present invention;

FIG. 2 is a schematic diagram of the first illustrative embodiment of the present invention;

FIG. 3 is a layout of the first illustrative embodiment of the present invention; and

FIG. 4 is a schematic diagram of a seconf illustrative embodiment of the present invention

DETAILED DESCRIPTION

FIG. 1 is a block diagram of an illustrative embodiment of the inpuit section of a power amplifier of the invention such as might be used in a cellular phone. The input section comprises a power amplifier stage 110 and a limiter circuit 120. Illustratively, the power amplifier stage comprises a heteroj unction bipolar transistopr (HBT) having an emitter, a base and a collector. The limiter circuit 120 comprises at least a first PHEMT or MESFET coupled between an RF signal input 130 and the base of the HBT. In addition, the limiter circuit may include one or more additional diode-connected PHEMTs or MESFETs coupled between the first PHEMT or MESFET and the collector of the HBT.

FIG. 2 is a schematic depicting an illustrative embodiment of the input section of a cellular power amplifier with the integrated RF limiter of FIG. 1. The power amplifier stage comprises HBT Q6 having an emitter, a base and a collector. The limiter circuitry comprises: first PHEMT M2, second and third PHEMTs M3 and M4 connected as diodes, DC blocking capacitors C16 and C13, gate resistor R11, drain to source resistor R13, drain to supply resistor (sum of R15, R12, R14), and resistor R16 in series with detector diodes PHEMT M3 and M4. PHEMT M4 is connected to the collector of HBT RF stage Q6.

With RF applied to “RFIN” in the normal operational input power range, M2 is biased to be in a fully on low loss state. When the input level reaches a certain power level determined by the combination of the diodes, resistors and the RF gain of the first stage (Q6), the source and drain voltage of M2 will increase to become more positive relative to the gate causing M2 to start pinching off or go into a high loss state.

FIG. 4 is a schematic drawing depicting an alternate implementation where the power amplifier architecture has two paths, high power and low power, using a SP2T switch. The high power path includes a power amplifier stage comprising HBT Q545, and a limiter circuit comprising diodes M1 and M3 and PHEMT M46. The low power path includes a power amplifier stage comprising HBT Q62; and a limiter circuit comprising detector diodes M4 and M5 and PHEMT M47. Detector diodes M1 and M3 and resistor R16 are used to raise the drain source voltage of PHEMT switch M46 for high power path and detector diodes M4 and M5 and resistor R15 similarly raise the drain source voltage for PHEMT M47 for the low power path.

As shown in FIG. 4, the diodes are implemented using diode coupled PHEMT. Alternatively, MESFETs could be used in place of the PHEMTs or Schottky barrier diodes could be used in place of the PHEMTs or MESFETs.

Illustratively, the HBT and field effect transistor (FET) devices are formed in a III-V semiconductor material such as Gallium Nitride, Indium Phosphide, or Gallium Arsenide/Indium Gallium Phosphide. In some applications, it may be advantageous to integrate the HBT and the FET device in a single semiconductor crystal by epitaxially growing the HBT device on an epitaxially grown FET device. Such a device and the process for making it in a GaAs/InGaP epitaxial growth process is described in U.S. Pat. No. 7,015,519, which is incorporated herein by reference. Other materials may also be used.

As will be apparent to those skilled in the art, numerous variations may be practiced within the spirit and scope of the present invention. 

1-24. (canceled)
 25. A power amplifier module comprising: a signal input; a power amplifier stage of a first power amplifier, the power amplifier stage of the first power amplifier including a first transistor; and a first limiter connected between the signal input and the power amplifier stage of the first power amplifier, the first limiter including at least a first pseudomorphic high electron mobility transistor connected to a base of the first transistor and a first diode connected to a collector of the first transistor.
 26. The power amplifier module of claim 25 wherein the first transistor is a heterojunction bipolar transistor.
 27. The power amplifier module of claim 25 wherein the power amplifier stage of the first power amplifier is formed in a III-V semiconductor material.
 28. The power amplifier module of claim 25 wherein the first limiter further includes a second diode connected in series to the first diode.
 29. The power amplifier module of claim 25 wherein the first diode is implemented by a second pseudomorphic high electron mobility transistor.
 30. The power amplifier module of claim 25 wherein the first diode is implemented by a metal-semiconductor field-effect transistor.
 31. The power amplifier module of claim 25 wherein the first diode is a Schottky barrier diode.
 32. The power amplifier module of claim 25 further comprising a power amplifier stage of a second power amplifier, the power amplifier of the second power amplifier including a second transistor, and the second power amplifier configured to support a different power level than the first power amplifier.
 33. The power amplifier module of claim 32 further comprising a second limiter connected between the signal input and the power amplifier stage of the second power amplifier.
 34. The power amplifier module of claim 33 wherein the second limiter includes at least a second pseudomorphic high electron mobility transistor connected to a base of the second transistor and a second diode connected to a collector of the second transistor.
 35. The power amplifier module of claim 32 further comprising a switch configured to select between a first path associated with the first power amplifier and a second path associated with the second power amplifier.
 36. The power amplifier module of claim 25 wherein the first limiter circuit is configured to attenuate a signal received at the signal input when an input power level satisfies a threshold.
 37. The power amplifier module of claim 25 wherein the first limiter further includes a direct current blocking capacitor connected to the first pseudomorphic high electron mobility transistor.
 38. A wireless device comprising: an antenna; and a power amplifier module including a signal input, a power amplifier stage of a first power amplifier, and a first limiter, the power amplifier stage of the first power amplifier including a first transistor, and the first limiter connected between the signal input and the power amplifier stage of the first power amplifier, and including at least a first pseudomorphic high electron mobility transistor connected to a base of the first transistor and a diode connected to a collector of the first transistor.
 39. The wireless device of claim 38 wherein the wireless device is a cellular phone.
 40. The wireless device of claim 38 wherein the diode is implemented by a second pseudomorphic high electron mobility transistor, is implemented by a metal-semiconductor field-effect transistor, or is a Schottky barrier diode.
 41. The wireless device of claim 38 wherein the power amplifier module further includes a power amplifier stage of a second power amplifier and a second limiter connected between the signal input and the power amplifier stage of the second power amplifier, the power amplifier of the second power amplifier including a second transistor, and the second power amplifier configured to support a different power level than the first power amplifier.
 42. The wireless device of claim 41 wherein the second limiter includes at least a second pseudomorphic high electron mobility transistor connected to a base of the second transistor and a second diode connected to a collector of the second transistor.
 43. The wireless device of claim 41 wherein the power amplifier module further includes a switch configured to select between a first path associated with the first power amplifier and a second path associated with the second power amplifier.
 44. The wireless device of claim 38 wherein the first limiter circuit attenuates a signal received at the signal input when an input power level satisfies a threshold. 